1. Field of the Invention
The present invention relates to a method for making a high temperature super-conducting field-effect transistor with a thick super-conducting channel layer.
2. Description of the Prior Art
Generally, a super-conducting transistor has widely used as an active device, which has a fast calculating speed, a fast data processing speed and a low-consumption power in characteristics thereof, and can be mainly embodied in a signal processing apparatus, such as a video signal processing system, a high-performance work-station, a satellite signal processing system, a super computer and the like.
FIG. 1 shows a construction of a prior art super-conducting field-effect transistor(hereinafter, referred to as "FET") having an-extremely thin super-conducting channel. In FIG. 1, the prior art super-conducting FET comprises a substrate 11 composed of YBa.sub.2 Cu.sub.3 O.sub.7-x, an extremely thin super-conducting channel 12 composed of an oxide superconductor thin film on the principal surface of the substrate 11, and an insulating layer 13 formed on the super-conducting channel 12. The FET further comprises source/drain electrodes 15 and 16 which are formed on both ends of the super-conducting channel layer 12 and formed of a metal, and a gate electrode 14 which is formed on the insulating layer 13 and formed of a metal. In this FET structure, the insulating layer 13 is formed of SrTiO.sub.3 and the super-conducting channel 12 is composed of a high temperature superconductor. This super-conducting FET is composed of a three-layer structure in which metal-insulator-high temperature superconductor layers are sequentially formed on the substrate 11, and is disclosed in European Patent Publication No. 0 533 519 A2.
FIG. 2 shows a construction of another prior art super-conducting FET with an inverted three-layer structure. The super-conducting FET of FIG. 2 comprises an SrTiO.sub.3 substrate 21 doped with Nb, a platinum layer 22 formed on a main surface of the substrate 21, and a super-conducting channel layer 24 formed above the platinum layer 22 with an insulating layer 23 formed therebetween. The super-conducting FET of FIG. 2 further comprises metal source/drain electrodes 25 and 26 which are formed on the super-conducting channel layer 24 and electrically isolated from each other, and a gate electrode 27 which is formed on the back surface of the substrate 21. This super-conducting FET of FIG. 2 has an inverted three-layer structure in comparison with the super-conducting FET of FIG. 1, and is disclosed in U.S. Pat. No. 5,278,138.
In these super-conducting FETs, however, since a high-temperature super-conducting film is utilized as a gate, there arises a serious problem that electric field effect is lowered within several percents.
Also, there are the reasons that high field electric effect can not be obtained in the prior art super-conducting FETs. One of the reasons is that an ultra-thin film having 100 .ANG. or less in thickness is embodied as a high-temperature super-conducting channel layer of the FET. In practical fabrication of the high-temperature super-conducting layer, there arises several problems.
First, in case of making a YBa.sub.2 CuO.sub.7-x super-conducting layer having extremely thin film, since the super-conducting layer reacts chemically on moisture in air and is decomposed at a very fast speed to be changed to other material, it loses a super-conducting characteristics thereof.
Secondly, in fabrication of the super-conducting transistor, since several steps of etching processes have to be carried out, an extremely thin super-conducting layer is seriously lowered in chemical stability.
Finally, if thickness of an extremely thin super-conducting layer is further thin, reproduction of such a super-conducting layer is seriously lowered because of a limit of an optimum range of a film formation condition.